The following descriptions and examples are given as background only.
Programmable non-volatile memories (NVM) are useful in many applications because they retain stored information even when power is removed from the memory. There are many different types of programmable non-volatile memory including, but not limited to, programmable read only memory (PROM), electrically erasable ROM (EEPROM) and Flash memory. These memory types have several methods of charge storage including but not limited to placing charge on a Floating Gate or Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) storage material or node. Like other types of memory, programmable NVMs are usually constructed as an array of bit cells arranged in rows and columns. Each bit cell may include one or two transistors (i.e., 1T or 2T cells). During programming, charge is injected into the storage node of one of the transistors. The injected charge remains in the storage node until the bit cell is erased.
Flash memory is a type of non-volatile memory, which uses a floating-gate bit cell structure. The bit cell includes at least one transistor (i.e., the floating gate transistor), which has both a control gate and a floating gate. The control gate is used to properly bias the transistor for reading, programming and erasing, while the floating gate is used as the storage node of the bit cell. The floating gate is arranged between the channel and control gate of the transistor. The floating gate is typically separated from the channel by a thin tunnel oxide and separated from the control gate by an Oxide-Nitride-Oxide (ONO) dielectric layer. The bit cell is programmed by applying charge to the floating gate, and erased by removing charge from the floating gate while the control gate is properly biased. During programming modes, charge is injected from the channel to the floating gate through the tunnel oxide. The method of injection may be through direct Fowler-Nordheim (FN) tunneling or Channel Hot Electron Injection (CHEI). Erasing is typically achieved by FN tunneling of the charge from the channel to the floating gate.
Interest in SONOS has increased in recent years because the scalability of floating gate NVM technology is reaching its limits. One of the challenges stems from isolating the floating gate from surrounding layers. When device dimensions shrink, the insulating layers surrounding the gate also shrink. This leads to increased capacitive coupling between memory bits and greater likelihood of small “pinhole” manufacturing defects in the insulating layers, creating a discharge path. The second challenge that arises from shrinking dimensions is the increasing mismatch between the voltage used to cause tunneling and the normal circuit operating voltage. As lithography shrinks, circuits operate at lower voltages to avoid damage, but the voltage used to induce tunneling does not drop proportionately. This makes it increasingly difficult to integrate erase and write circuitry into the rest of the memory device. The voltage mismatch also increases the likelihood of long term damage to the floating gate transistor with each write/erase cycle, an effect known as “wear out.”